Today we are moving towards ultra-deep sub micron technology nodes in the quest to incorporate more features into a small device, but at the same time both the system and silicon complexities are increasing day by day. In-order to overcome these, there should be a well-defined flow to meet the time to market without compromising on the quality.

Adapting to the latest tools and trends in the current day market, we deliver the customer small die area, low power dissipation and highest performance. Sasken provides the Netlist-to-GDSII services to customer in following three distinct Phases:

Phase-1: Initial Analysis
This is the first drop of the netlist from customer where Sasken performs Die-size/power Estimation, IO Ring sign-off

Phase-2: Trial Tapeout
This is the penultimate drop of the netlist from customer where Sasken performs 90% design closure with clear understanding of issues for the non-closed items

Phase-3: Tape-Out
This is the Final drop of the netlist from customer where Sasken signs-off on the Design & extracts GDSII to be released to Foundry.

Here are important milestones of Sasken’s Project life cycle.

Design requirements to kick off:
We do an extensive number of checks to find the correctness of technology and library data. Also variety of checks on the incoming netlist & constraints are performed to discover any possible issue in the earlier stages and provide a quantitative feedback to the customer to make the required changes.

Design Planning:
Design planning is an important aspect in the overall physical implementation flow. A good floorplan considering various macro, standard cells and IO connectivity really helps to achieve good QOR. With the present day low power requirements in mind, we also employ various power reduction techniques like Multi-Vt cells usage, Clock gating, multi voltage domains, power gating etc. Though the floorplan constraints are provided by the designers/customers, the implementation tool has to be stretched and directed at the various stages of the flow.

Sasken performs IO planning, floor planning, partitioning the design into manageable blocks, power planning/optimizations, pre-layout timing optimizations, and early silicon performance analysis.

Design Implementation:
This is the phase, which needs proven methodology & expertise to minimize time consuming and costly iterations. Placement of standard cells, clock tree implementation and optimizations, post CTS optimizations, SI and crosstalk aware routing, post route optimizations, timing analysis & closure, cross talk delay & noise closure, spare cell insertion will be carried out prudently. Our timing team performs the correlation of timing and design rule checks with the P&R tool and signoff tool and we apply corresponding margins so that issues can be confronted and resolved at the initial stages itself.

We have proven expertise in design & development of flow automation scripts using perl, Tcl for various activities that ensures repeatability and avoids human errors.

Design Signoff:
The quality of the tapeout is guaranteed only when the checks pass the Industry signoff tools. We signoff checks like LVS/DRC, Antenna, Static & dynamic power, Signal EM, cross talk delay/noise, ERC, STA, logic equivalence checks with the Industry standard tools.

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