Sasken ensures the delivery of fully tested silicon by way of:

• Rich experience in DFT flow using the industry standard DFT tool suite and also in handling all DFT aspects like Scan, BIST, JTAG for multimillion gate ASICs and SOCs
• Providing DFT services for each stage of the design cycle (RTL, pre-layout and post-layout)
• Experience in test vector generation, verification and hand-off for silicon
• Close interaction with physical design, synthesis and STA teams for reducing number of iterations
• Library and hard macro sanity check
• Developing necessary scripting and automation
• Comprehensive test plans with detailed test methodology as per customer requirements
• Top-level ATPG fault-coverage analysis and ATPG and MBIST pattern generation and verification
• Final tester format generation and verification with post- route net list