Sasken provides high-quality physical design services to address the challenges of semiconductor companies. Our expertise lies in:

• Time-proven project planning methodology
• Library and hard macro sanity check
• Floor planning, block placement, package planning, IO placement, power planning and net ordering for tackling SI issues
• Clock tree planning and expansion- automated or manual, based on clock skew and data skew balancing requirements
• Routing – positionally critical nets, timing critical nets, SI aware topology planning
• Corrections based on EM, IR, Process Antenna Effects, OCV and Jitter
• Physical verification involving adherence checks for design rules, density, slotting, antenna rules and LVS
• Use of different statistics and design metrics generated along the flow to provide insight about design